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CY7C1461AV33 CY7C1463AV33 CY7C1465AV33
36-Mbit (1M x 36/2 M x 18/512K x 72) Flow-Through SRAM with NoBLTM Architecture
Features
* No Bus LatencyTM (NoBLTM) architecture eliminates dead cycles between write and read cycles * Supports up to 133-MHz bus operations with zero wait states -- Data is transferred on every clock * Pin-compatible and functionally equivalent to ZBTTM devices * Internally self timed output buffer control to eliminate the need to use OE * Registered inputs for flow through operation * Byte Write capability * 3.3V/2.5V IO power supply * Fast clock-to-output times -- 6.5 ns (for 133-MHz device) * Clock Enable (CEN) pin to enable clock and suspend operation * Synchronous self timed writes * Asynchronous Output Enable * CY7C1461AV33, CY7C1463AV33 available in JEDEC-standard Pb-free 100-pin TQFP package, Pb-free and non-Pb-free 165-Ball FBGA package. CY7C1465AV33 available in Pb-free and non-Pb-free 209-Ball FBGA package * Three chip enables for simple depth expansion * Automatic Power down feature available using ZZ mode or CE deselect * IEEE 1149.1 JTAG-Compatible Boundary Scan * Burst Capability -- linear or interleaved burst order * Low standby power
Functional Description[1]
The CY7C1461AV33/CY7C1463AV33/CY7C1465AV33 is a 3.3V, 1M x 36/2M x 18/512K x 72 Synchronous Flow -through Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1461AV33/CY7C1463AV33/CY7C1465AV33 is equipped with the advanced No Bus Latency (NoBL) logic required to enable consecutive Read/Write operations with data being transferred on every clock cycle. This feature dramatically improves the throughput of data through the SRAM, especially in systems that require frequent Write-Read transitions. All synchronous inputs pass through input registers controlled by the rising edge of the clock. The clock input is qualified by the Clock Enable (CEN) signal, which when deasserted suspends operation and extends the previous clock cycle. Maximum access delay from the clock rise is 6.5 ns (133-MHz device). Write operations are controlled by the two or four Byte Write Select (BWX) and a Write Enable (WE) input. All writes are conducted with on-chip synchronous self timed write circuitry. Three synchronous Chip Enables (CE1, CE2, CE3) and an asynchronous Output Enable (OE) provide for easy bank selection and output tri-state control. To avoid bus contention, the output drivers are synchronously tri-stated during the data portion of a write sequence.
Selection Guide
133 MHz Maximum Access Time Maximum Operating Current Maximum CMOS Standby Current 6.5 310 120 100 MHz 8.5 290 120 Unit ns mA mA
Note: 1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.
Cypress Semiconductor Corporation Document #: 38-05356 Rev. *F
*
198 Champion Court
*
San Jose, CA 95134-1709
* 408-943-2600 Revised July 09, 2007
CY7C1461AV33 CY7C1463AV33 CY7C1465AV33
Logic Block Diagram - CY7C1461AV33 (1M x 36)
A0, A1, A MODE CLK CEN C CE ADV/LD C WRITE ADDRESS REGISTER ADDRESS REGISTER A1 D1 A0 D0
BURST LOGIC
Q1 A1' A0' Q0
ADV/LD BW A BW B BW C BW D WE WRITE REGISTRY AND DATA COHERENCY CONTROL LOGIC WRITE DRIVERS MEMORY ARRAY
S E N S E A M P S
D A T A S T E E R I N G
O U T P U T B U F F E R S E
DQs DQP A DQP B DQP C DQP D
OE CE1 CE2 CE3 ZZ
INPUT REGISTER READ LOGIC
E
SLEEP CONTROL
Logic Block Diagram - CY7C1463AV33 (2M x 18)
A0, A1, A MODE CLK CEN C CE ADV/LD C WRITE ADDRESS REGISTER ADDRESS REGISTER A1 D1 A0 D0
BURST LOGIC
Q1 A1' A0' Q0
ADV/LD BW A BW B WRITE REGISTRY AND DATA COHERENCY CONTROL LOGIC WRITE DRIVERS MEMORY ARRAY
S E N S E A M P S
D A T A S T E E R I N G
O U T P U T B U F F E R S E
DQs DQP A DQP B
WE
OE CE1 CE2 CE3 ZZ
INPUT REGISTER READ LOGIC
E
SLEEP CONTROL
Document #: 38-05356 Rev. *F
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CY7C1461AV33 CY7C1463AV33 CY7C1465AV33
Logic Block Diagram - CY7C1465AV33 (512K x 72)
A0, A1, A MODE
CLK CEN
ADDRESS REGISTER 0
A1 A1' D1 Q1 A0 A0' BURST D0 Q0 LOGIC ADV/LD C
C
WRITE ADDRESS REGISTER 1
WRITE ADDRESS REGISTER 2
ADV/LD BW a BW b BW c BW d BW e BW f BW g BW h
WRITE DRIVERS
MEMORY ARRAY
S E N S E A M P S
O U T P U T R E G I S T E R S
D A T A S T E E R I N G
O U T P U T B U F F E R S
WRITE REGISTRY AND DATA COHERENCY CONTROL LOGIC
E
E
DQ s DQ Pa DQ Pb DQ Pc DQ Pd DQ Pe DQ Pf DQ Pg DQ Ph
WE
INPUT REGISTER 1
E
INPUT REGISTER 0
E
OE CE1 CE2 CE3
ZZ
READ LOGIC
Sleep Control
Document #: 38-05356 Rev. *F
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CY7C1461AV33 CY7C1463AV33 CY7C1465AV33
Pin Configurations 100-Pin TQFP Pinout
ADV/LD
BWD
BWC
BWB
BWA
CE1
CE2
CE3
VDD
VSS
CEN
CLK
WE
OE
A 82
A
100
A
99
A
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
A
BYTE C
BYTE D
DQPC DQC DQC VDDQ VSS DQC DQC DQC DQC VSS VDDQ DQC DQC NC VDD NC VSS DQD DQD VDDQ VSS DQD DQD DQD DQD VSS VDDQ DQD DQD DQPD
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
31 32 33 34 35 36
81
A
CY7C1461AV33
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
44 45 46 47 48 49 50
DQPB DQB DQB VDDQ VSS DQB DQB DQB DQB VSS VDDQ DQB DQB VSS NC VDD ZZ DQA DQA VDDQ VSS DQA DQA DQA DQA VSS VDDQ DQA DQA DQPA
BYTE B
BYTE A
37
38
39
40
41
42 NC/72M
A1
A0
VSS
MODE
NC/288M
NC/144M
VDD
A
A
A
A
43
A
A
A
Document #: 38-05356 Rev. *F
A
A
A
A
A
Page 4 of 31
CY7C1461AV33 CY7C1463AV33 CY7C1465AV33
Pin Configurations (continued) 100-Pin TQFP Pinout
ADV/LD
BWB
BWA
CE1
CE2
CE3
VDD
VSS
CEN
CLK
WE
OE
NC
NC
A 82
100
A
99
A
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
A
83
A
NC NC NC VDDQ VSS NC NC DQB DQB VSS VDDQ DQB DQB NC VDD NC VSS DQB DQB VDDQ VSS DQB DQB DQPB NC VSS VDDQ NC NC NC
BYTE B
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
31 32 33 34 35 36
81
A
CY7C1463AV33
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
44 45 46 47 48 49 50
A NC NC VDDQ VSS NC DQPA DQA DQA VSS VDDQ DQA DQA VSS NC VDD ZZ DQA DQA VDDQ VSS DQA DQA NC NC VSS VDDQ NC NC NC
BYTE A
37
38
39
40
41
42
A1
A0
VSS
MODE
VDD
A
A
A
A
43
A
A
A
NC/288M
NC/144M
NC/72M
Document #: 38-05356 Rev. *F
A
A
A
A
A
Page 5 of 31
CY7C1461AV33 CY7C1463AV33 CY7C1465AV33
Pin Configurations (continued) 165-Ball FBGA (15 x 17 x 1.4 mm) Pinout CY7C1461AV33 (1M x 36)
1 A B C D E F G H J K L M N P R
NC/576M NC/1G DQPC DQC DQC DQC DQC NC DQD DQD DQD DQD DQPD MODE
2
A A NC DQC DQC DQC DQC NC DQD DQD DQD DQD NC A
3
CE1 CE2 VDDQ VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A A
4
BWC BWD VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS
A
5
BWB BWA VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC TDI
TMS
6
CE3 CLK
7
CEN WE
8
ADV/LD OE
9
A A VDDQ VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A
A
10
A
11
NC NC DQPB DQB DQB DQB DQB ZZ DQA DQA DQA DQA DQPA NC/288M A
A NC DQB DQB DQB DQB NC DQA DQA DQA DQA NC A A
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC A1 A0
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC TDO TCK
VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS
A
NC/144M NC/72M
A
A
CY7C1463AV33 (2M x 18)
1 A B C D E F G H J K L M N P R
NC/576M NC/1G NC NC NC NC NC NC DQB DQB DQB DQB DQPB MODE
2
A A NC DQB DQB DQB DQB NC NC NC NC NC NC A
3
CE1 CE2 VDDQ VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A A
4
BWB NC VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS
A
5
NC BWA VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC TDI
TMS
6
CE3 CLK
7
CEN WE
8
ADV/LD OE
9
A A VDDQ VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A
A
10
A
11
A NC DQPA DQA DQA DQA DQA ZZ NC NC NC NC NC NC/288M A
A NC NC NC NC NC NC DQA DQA DQA DQA NC A A
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC A1 A0
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC TDO TCK
VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS
A
NC/144M NC/72M
A
A
Document #: 38-05356 Rev. *F
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CY7C1461AV33 CY7C1463AV33 CY7C1465AV33
Pin Configurations (continued) 209-Ball FBGA (14 x 22 x 1.76 mm) Pinout CY7C1465AV33 (512K x 72)
1 A B C D E F G H J K L M N P R T U V W
DQg DQg DQg DQg DQPg DQc DQc DQc DQc NC DQh DQh DQh DQh DQPd DQd DQd DQd DQd
2
DQg DQg DQg DQg DQPc DQc DQc DQc DQc NC DQh DQh DQh DQh DQPh DQd DQd DQd DQd
3
A BWSc BWSh VSS VDDQ VSS VDDQ VSS VDDQ CLK VDDQ VSS VDDQ VSS VDDQ VSS NC/144M A TMS
4
CE2 BWSg
5
A NC
6
ADV/LD WE CE1 OE VDD NC NC NC NC CEN NC NC NC ZZ VDD MODE A A1 A0
7
A A NC NC VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD NC A A A
8
CE3 BWSb BWSe NC VDDQ VSS VDDQ VSS VDDQ NC VDDQ VSS VDDQ VSS VDDQ NC A A TDO
9
A BWSf BWSa VSS VDDQ VSS VDDQ VSS VDDQ NC VDDQ VSS VDDQ VSS VDDQ VSS NC/288M A TCK
10
DQb DQb DQb DQb DQPf DQf DQf DQf DQf NC DQa DQa DQa DQa DQPa DQe DQe DQe DQe
11
DQb DQb DQb DQb DQPb DQf DQf DQf DQf NC DQa DQa DQa DQa DQPe DQe DQe DQe DQe
BWSd NC/576M NC VDDQ VSS VDDQ VSS VDDQ NC VDDQ VSS VDDQ VSS VDDQ NC A A TDI NC/1G VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD NC NC/72M A A
Document #: 38-05356 Rev. *F
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CY7C1461AV33 CY7C1463AV33 CY7C1465AV33
Pin Definitions
Name A0, A1, A BWA, BWB BWC, BWD, BWE, BWF, BWG, BWH WE ADV/LD IO Description InputAddress Inputs used to select one of the address locations. Sampled at the rising edge of the Synchronous CLK. A[1:0] are fed to the two-bit burst counter. InputByte Write Inputs, Active LOW. Qualified with WE to conduct writes to the SRAM. Sampled on Synchronous the rising edge of CLK.
InputWrite Enable Input, Active LOW. Sampled on the rising edge of CLK if CEN is active LOW. This Synchronous signal must be asserted LOW to initiate a write sequence. InputAdvance/Load Input. Used to advance the on-chip address counter or load a new address. When Synchronous HIGH (and CEN is asserted LOW) the internal burst counter is advanced. When LOW, a new address can be loaded into the device for an access. After being deselected, ADV/LD must be driven LOW to load a new address. InputClock Clock Input. Used to capture all synchronous inputs to the device. CLK is qualified with CEN. CLK is only recognized if CEN is active LOW.
CLK CE1 CE2 CE3 OE
InputChip Enable 1 Input, Active LOW. Sampled on the rising edge of CLK. Used in conjunction with Synchronous CE2 and CE3 to select/deselect the device. InputChip Enable 2 Input, Active HIGH. Sampled on the rising edge of CLK. Used in conjunction with Synchronous CE1 and CE3 to select/deselect the device. InputChip Enable 3 Input, Active LOW. Sampled on the rising edge of CLK. Used in conjunction with Synchronous CE1 and CE2 to select/deselect the device. InputOutput Enable, asynchronous input, Active LOW. Combined with the synchronous logic block Asynchronous inside the device to control the direction of the IO pins. When LOW, the IO pins are allowed to behave as outputs. When deasserted HIGH, IO pins are tri-stated, and act as input data pins. OE is masked during the data portion of a write sequence, during the first clock when emerging from a deselected state, when the device is deselected. InputClock Enable Input, Active LOW. When asserted LOW the Clock signal is recognized by the Synchronous SRAM. When deasserted HIGH the Clock signal is masked. Since deasserting CEN does not deselect the device, use CEN to extend the previous cycle when required. InputZZ "Sleep" Input. This active HIGH input places the device in a non-time critical "sleep" condition Asynchronous with data integrity preserved. During normal operation, this pin has to be LOW or left floating. ZZ pin has an internal pull down. IOBidirectional Data IO lines. As inputs, they feed into an on-chip data register that is triggered by Synchronous the rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by the addresses presented during the previous clock rise of the read cycle. The direction of the pins is controlled by OE. When OE is asserted LOW, the pins behave as outputs. When HIGH, DQs and DQP[A:D] are placed in a tri-state condition.The outputs are automatically tri-stated during the data portion of a write sequence, during the first clock when emerging from a deselected state, and when the device is deselected, regardless of the state of OE. IOBidirectional Data Parity IO Lines. Functionally, these signals are identical to DQs. During write Synchronous sequences, DQPX is controlled by BWX correspondingly. Input Strap Pin Mode Input. Selects the burst order of the device. When tied to Gnd selects linear burst sequence. When tied to VDD or left floating selects interleaved burst sequence. Power Supply Power supply inputs to the core of the device. IO Power Supply Ground Power supply for the IO circuitry. Ground for the device.
CEN
ZZ
DQs
DQPX MODE
VDD VDDQ VSS
Document #: 38-05356 Rev. *F
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CY7C1461AV33 CY7C1463AV33 CY7C1465AV33
Pin Definitions (continued)
Name TDO IO Description JTAG serial Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK. If the JTAG feature is not used, leave this pin unconnected. This pin is not available on TQFP packages. output Synchronous JTAG serial Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG feature is not being used, this pin can be left floating or connected to VDD through a pull up resistor. This pin is input Synchronous not available on TQFP packages. JTAG serial Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG feature is not input being used, this pin can be disconnected or connected to VDD. This pin is not available on TQFP Synchronous packages. JTAG-Clock N/A N/A N/A N/A N/A N/A Clock input to the JTAG circuitry. If the JTAG feature is not being used, this pin must be connected to VSS. This pin is not available on TQFP packages. No Connects. Not internally connected to the die. Not connected to the die. Can be tied to any voltage level. Not connected to the die. Can be tied to any voltage level. Not connected to the die. Can be tied to any voltage level. Not connected to the die. Can be tied to any voltage level. Not connected to the die. Can be tied to any voltage level. * CE1, CE2, and CE3 are ALL asserted active * The Write Enable input signal WE is deasserted HIGH * ADV/LD is asserted LOW. The address presented to the address inputs is latched into the Address Register and presented to the memory array and control logic. The control logic determines that a read access is in progress and allows the requested data to propagate to the output buffers. The data is available within 6.5 ns (133-MHz device) provided OE is active LOW. After the first clock of the read access, the output buffers are controlled by OE and the internal control logic. OE must be driven LOW in order for the device to drive out the requested data. On the subsequent clock, another operation (Read/Write/Deselect) can be initiated. When the SRAM is deselected at clock rise by one of the chip enable signals, its output is tri-stated immediately. Burst Read Accesses The CY7C1461AV33/CY7C1463AV33/CY7C1465AV33 has an on-chip burst counter that allows the user the ability to supply a single address and conduct up to four Reads without reasserting the address inputs. ADV/LD must be driven LOW to load a new address into the SRAM, as described in the Single Read Access section above. The sequence of the burst counter is determined by the MODE input signal. A LOW input on MODE selects a linear burst mode, a HIGH selects an interleaved burst sequence. Both burst counters use A0 and A1 in the burst sequence, and wraps around when incremented sufficiently. A HIGH input on ADV/LD increments the internal burst counter regardless of the state of chip enable inputs or WE. WE is latched at the beginning of a burst cycle. Therefore, the type of access (Read or Write) is maintained throughout the burst sequence. Page 9 of 31
TDI
TMS
TCK NC NC/72M
NC/144M NC/288M NC/576M NC/1G
Functional Overview
The CY7C1461AV33/CY7C1463AV33/CY7C1465AV33 is a synchronous flow through burst SRAM designed specifically to eliminate wait states during Write-Read transitions. All synchronous inputs pass through input registers controlled by the rising edge of the clock. The clock signal is qualified with the Clock Enable input signal (CEN). If CEN is HIGH, the clock signal is not recognized and all internal states are maintained. All synchronous operations are qualified with CEN. Maximum access delay from the clock rise (tCDV) is 6.5 ns (133-MHz device). Accesses can be initiated by asserting all three Chip Enables (CE1, CE2, CE3) active at the rising edge of the clock. If Clock Enable (CEN) is active LOW and ADV/LD is asserted LOW, the address presented to the device is latched. The access can either be a read or write operation, depending on the status of the Write Enable (WE). BWX can be used to conduct byte write operations. Write operations are qualified by the Write Enable (WE). All writes are simplified with on-chip synchronous self timed write circuitry. Three synchronous Chip Enables (CE1, CE2, CE3) and an asynchronous Output Enable (OE) simplify depth expansion. All operations (Reads, Writes, and Deselects) are pipelined. ADV/LD must be driven LOW after the device has been deselected to load a new address for the next operation. Single Read Accesses A read access is initiated when these conditions are satisfied at clock rise: * CEN is asserted LOW
Document #: 38-05356 Rev. *F
CY7C1461AV33 CY7C1463AV33 CY7C1465AV33
Single Write Accesses Write access are initiated when the following conditions are satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2, and CE3 are ALL asserted active, and (3) the write signal WE is asserted LOW. The address presented to the address bus is loaded into the Address Register. The write signals are latched into the Control Logic block. The data lines are automatically tri-stated regardless of the state of the OE input signal. This allows the external logic to present the data on DQs and DQPX. On the next clock rise the data presented to DQs and DQPX (or a subset for byte write operations, see truth table for details) inputs is latched into the device and the write is complete. Additional accesses (Read/Write/Deselect) can be initiated on this cycle. The data written during the Write operation is controlled by BWX signals. The CY7C1461AV33/CY7C1463AV33/CY7C1465AV33 provides byte write capability that is described in the truth table. Asserting the Write Enable input (WE) with the selected Byte Write Select input selectively writes to only the desired bytes. Bytes not selected during a byte write operation remains unaltered. A synchronous self timed write mechanism has been provided to simplify the write operations. Byte write capability has been included to greatly simplify Read/Modify/Write sequences, which can be reduced to simple byte write operations. Because the CY7C1461AV33/CY7C1463AV33/CY7C1465AV33 is a common IO device, data must not be driven into the device while the outputs are active. The Output Enable (OE) can be deasserted HIGH before presenting data to the DQs and DQPX inputs. Doing so tri-states the output drivers. As a safety precaution, DQs and DQPX are automatically tri-stated during the data portion of a write cycle, regardless of the state of OE. Burst Write Accesses The CY7C1461AV33/CY7C1463AV33/CY7C1465AV33 has an on-chip burst counter that allows the user the ability to supply a single address and conduct up to four Write operations without reasserting the address inputs. ADV/LD must be driven LOW to load the initial address, as described in the Single Write Access section above. When ADV/LD is driven HIGH on the subsequent clock rise, the Chip Enables (CE1, CE2, and CE3) and WE inputs are ignored and the burst counter is incremented. The correct BWX inputs must be driven in each cycle of the burst write, to write the correct bytes of data.
Interleaved Burst Address Table (MODE = Floating or VDD)
.
First Address A1: A0 00 01 10 11
Second Address A1: A0 01 00 11 10
Third Address A1: A0 10 11 00 01
Fourth Address A1: A0 11 10 01 00
Linear Burst Address Table (MODE = GND)
First Address A1: A0 00 01 10 11 Sleep Mode The ZZ input pin is an asynchronous input. Asserting ZZ places the SRAM in a power conservation "sleep" mode. Two clock cycles are required to enter into or exit from this "sleep" mode. While in this mode, data integrity is guaranteed. Accesses pending when entering the "sleep" mode are not considered valid nor is the completion of the operation guaranteed. The device must be deselected prior to entering the "sleep" mode. CE1, CE2, and CE3, must remain inactive for the duration of tZZREC after the ZZ input returns LOW. Second Address A1: A0 01 10 11 00 Third Address A1: A0 10 11 00 01 Fourth Address A1: A0 11 00 01 10
ZZ Mode Electrical Characteristics
Parameter IDDZZ tZZS tZZREC tZZI tRZZI Description Sleep mode standby current Device operation to ZZ ZZ recovery time ZZ active to sleep current ZZ Inactive to exit sleep current Test Conditions ZZ > VDD - 0.2V ZZ > VDD - 0.2V ZZ < 0.2V This parameter is sampled This parameter is sampled 0 2tCYC 2tCYC Min Max 100 2tCYC Unit mA ns ns ns ns
Document #: 38-05356 Rev. *F
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CY7C1461AV33 CY7C1463AV33 CY7C1465AV33
Truth Table[2, 3, 4, 5, 6, 7, 8]
Operation Deselect Cycle Deselect Cycle Deselect Cycle Continue Deselect Cycle Read Cycle (Begin Burst) Read Cycle (Continue Burst) NOP/Dummy Read (Begin Burst) Dummy Read (Continue Burst) Write Cycle (Begin Burst) Write Cycle (Continue Burst) NOP/Write Abort (Begin Burst) Write Abort (Continue Burst) Ignore Clock Edge (Stall) Sleep Mode Address Used None None None None External Next External Next External Next None Next Current None CE1 H X X X L X L X L X L X X X CE2 X X L X H X H X H X H X X X CE3 X H X X L X L X L X L X X X ZZ L L L L L L L L L L L L L H ADV/LD WE L L L H L H L H L H L H X X X X X X H X H X L X L X X X BWX X X X X X X X X L L H H X X OE X X X X L L H H X X X X X X CEN CLK L L L L L L L L L L L L H X L->H L->H L->H L->H DQ Tri-State Tri-State Tri-State Tri-State
L->H Data Out (Q) L->H Data Out (Q) L->H L->H Tri-State Tri-State
L->H Data In (D) L->H Data In (D) L->H L->H L->H X Tri-State Tri-State - Tri-State
Notes: 2. X = "Don't Care." H = Logic HIGH, L = Logic LOW. BWx = L signifies at least one Byte Write Select is active, BWx = Valid signifies that the desired byte write selects are asserted, see truth table for details. 3. Write is defined by BWX, and WE. See truth table for Read/Write. 4. When a write cycle is detected, all IOs are tri-stated, even during byte writes. 5. The DQs and DQPX pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock. 6. CEN = H, inserts wait states. 7. Device powers up deselected and the IOs in a tri-state condition, regardless of OE. 8. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle DQs and DQPX = Tri-state when OE is inactive or when the device is deselected, and DQs and DQPX = data when OE is active.
Document #: 38-05356 Rev. *F
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CY7C1461AV33 CY7C1463AV33 CY7C1465AV33
Truth Table for Read/Write[2, 9]
Function (CY7C1461AV33) Read Write No bytes written Write Byte A - (DQA and DQPA) Write Byte B - (DQB and DQPB) Write Byte C - (DQC and DQPC) Write Byte D - (DQD and DQPD) Write All Bytes WE H L L L L L L BWA X H L H H H L BWB X H H L H H L BWC X H H H L H L BWD X H H H H L L
Truth Table for Read/Write[2, 9]
Function (CY7C1463AV33) Read Write - No Bytes Written Write Byte a - (DQa and DQPa) Write Byte b - (DQb and DQPb) Write Both Bytes WE H L L L L BWb X H H L L BWa X H L H L
Truth Table for Read/Write[2, 9]
Function (CY7C1465AV33) Read Write - No Bytes Written Write Byte X - (DQx and DQPx) Write All Bytes WE H L L L BWx X H L All BW = L
Note: 9. Table only lists a partial listing of the byte write combinations. Any Combination of BWX is valid Appropriate write is done based on which byte write is active
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IEEE 1149.1 Serial Boundary Scan (JTAG)
The CY7C1461AV33/CY7C1463AV33/CY7C1465AV33 incorporates a serial boundary scan test access port (TAP). This part is fully compliant with 1149.1. The TAP operates using JEDEC-standard 3.3V/2.5V IO logic level. The CY7C1461AV33/CY7C1463AV33/CY7C1465AV33 contains a TAP controller, instruction register, boundary scan register, bypass register, and ID register. Disabling the JTAG Feature It is possible to operate the SRAM without using the JTAG feature. To disable the TAP controller, TCK must be tied LOW (VSS) to prevent clocking of the device. TDI and TMS are internally pulled up and may be unconnected. They may alternately be connected to VDD through a pull up resistor. TDO must be left unconnected. Upon power up, the device is up in a reset state which does not interfere with the operation of the device. Test Data In (TDI) The TDI ball is used to serially input information into the registers and can be connected to the input of any of the registers. The register between TDI and TDO is chosen by the instruction that is loaded into the TAP instruction register. TDI is internally pulled up and can be unconnected if the TAP is unused in an application. TDI is connected to the most significant bit (MSB) of any register. (See Tap Controller Block Diagram.) Test Data Out (TDO) The TDO output ball is used to serially clock data-out from the registers. The output is active depending upon the current state of the TAP state machine. The output changes on the falling edge of TCK. TDO is connected to the least significant bit (LSB) of any register. (See Tap Controller State Diagram.)
TAP Controller Block Diagram
0 Bypass Register
210
TAP Controller State Diagram
1 TEST-LOGIC RESET 0 0 RUN-TEST/ IDLE 1 SELECT DR-SCAN 0 1 CAPTURE-DR 0 SHIFT-DR 1 EXIT1-DR 0 PAUSE-DR 1 0 EXIT2-DR 1 UPDATE-DR 1 0 0 0 1 0 1 1 SELECT IR-SCAN 0 CAPTURE-IR 0 SHIFT-IR 1 EXIT1-IR 0 PAUSE-IR 1 EXIT2-IR 1 UPDATE-IR 1 0 0 1 0 1
TDI
Selection Circuitry
Instruction Register
31 30 29 . . . 2 1 0
Selection Circuitry
TDO
Identification Register
x. . . . .210
Boundary Scan Register
TCK TMS
TAP CONTROLLER
Performing a TAP Reset A RESET is performed by forcing TMS HIGH (VDD) for five rising edges of TCK. This RESET does not affect the operation of the SRAM and may be performed while the SRAM is operating. At power up, the TAP is reset internally to ensure that TDO comes up in a High-Z state.
The 0/1 next to each state represents the value of TMS at the rising edge of TCK. Test Access Port (TAP) Test Clock (TCK) The test clock is used only with the TAP controller. All inputs are captured on the rising edge of TCK. All outputs are driven from the falling edge of TCK. Test Mode Select (TMS) The TMS input is used to give commands to the TAP controller and is sampled on the rising edge of TCK. It is allowable to leave this ball unconnected if the TAP is not used. The ball is pulled up internally, resulting in a logic HIGH level.
TAP Registers Registers are connected between the TDI and TDO balls and allow data to be scanned into and out of the SRAM test circuitry. Only one register can be selected at a time through the instruction register. Data is serially loaded into the TDI ball on the rising edge of TCK. Data is output on the TDO ball on the falling edge of TCK. Instruction Register Three-bit instructions can be serially loaded into the instruction register. This register is loaded when it is placed between the TDI and TDO balls as shown in the Tap Controller Block Diagram. Upon power up, the instruction register is loaded with the IDCODE instruction. It is also loaded with the IDCODE instruction if the controller is placed in a reset state as described in the previous section. Page 13 of 31
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When the TAP controller is in the Capture-IR state, the two least significant bits are loaded with a binary "01" pattern to allow for fault isolation of the board-level serial test data path. Bypass Register To save time when serially shifting data through registers, it is sometimes advantageous to skip certain chips. The bypass register is a single-bit register that can be placed between the TDI and TDO balls. This allows data to be shifted through the SRAM with minimal delay. The bypass register is set LOW (VSS) when the BYPASS instruction is executed. Boundary Scan Register The boundary scan register is connected to all the input and bidirectional balls on the SRAM. The length of the Boundary Scan Register for the SRAM in different packages is listed in the Scan Register Sizes table. The boundary scan register is loaded with the contents of the RAM IO ring when the TAP controller is in the Capture-DR state and is then placed between the TDI and TDO balls when the controller is moved to the Shift-DR state. The EXTEST, SAMPLE/PRELOAD and SAMPLE Z instructions can be used to capture the contents of the IO ring. The Boundary Scan Order tables show the order in which the bits are connected. Each bit corresponds to one of the bumps on the SRAM package. The MSB of the register is connected to TDI, and the LSB is connected to TDO. Identification (ID) Register The ID register is loaded with a vendor-specific, 32-bit code during the Capture-DR state when the IDCODE command is loaded in the instruction register. The IDCODE is hardwired into the SRAM and can be shifted out when the TAP controller is in the Shift-DR state. The ID register has a vendor code and other information described in the Identification Register Definitions table. TAP Instruction Set Overview Eight different instructions are possible with the three bit instruction register. All combinations are listed in the Instruction Codes table. Three of these instructions are listed as RESERVED and must not be used. The other five instructions are described in detail below. Instructions are loaded into the TAP controller during the Shift-IR state when the instruction register is placed between TDI and TDO. During this state, instructions are shifted through the instruction register through the TDI and TDO balls. To execute the instruction after it is shifted in, the TAP controller needs to be moved into the Update-IR state. IDCODE The IDCODE instruction causes a vendor-specific, 32-bit code to be loaded into the instruction register. It also places the instruction register between the TDI and TDO balls and allows the IDCODE to be shifted out of the device when the TAP controller enters the Shift-DR state. The IDCODE instruction is loaded into the instruction register upon power up or whenever the TAP controller is supplied a test logic reset state. SAMPLE Z The SAMPLE Z instruction causes the boundary scan register to be connected between the TDI and TDO pins when the TAP controller is in a Shift-DR state. The SAMPLE Z command puts the output bus into a High-Z state until the next command is supplied during the "Update IR" state. SAMPLE/PRELOAD SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When the SAMPLE/PRELOAD instructions are loaded into the instruction register and the TAP controller is in the Capture-DR state, a snapshot of data on the inputs and output pins is captured in the boundary scan register. The user must be aware that the TAP controller clock can only operate at a frequency up to 20 MHz, while the SRAM clock operates more than an order of magnitude faster. Because there is a large difference in the clock frequencies, it is possible that during the Capture-DR state, an input or output undergoes a transition. The TAP may then try to capture a signal while in transition (metastable state). This does not harm the device, but there is no guarantee as to the value that is captured. Repeatable results may not be possible. To guarantee that the boundary scan register captures the correct value of a signal, the SRAM signal must be stabilized long enough to meet the TAP controller's capture setup plus hold times (tCS and tCH). The SRAM clock input might not be captured correctly if there is no way in a design to stop (or slow) the clock during a SAMPLE/PRELOAD instruction. If this is an issue, it is still possible to capture all other signals and simply ignore the value of the CK and CK captured in the boundary scan register. Once the data is captured, it is possible to shift out the data by putting the TAP into the Shift-DR state. This places the boundary scan register between the TDI and TDO pins. PRELOAD allows an initial data pattern to be placed at the latched parallel outputs of the boundary scan register cells prior to the selection of another boundary scan test operation. The shifting of data for the SAMPLE and PRELOAD phases can occur concurrently when required--that is, while data captured is shifted out, the preloaded data can be shifted in. BYPASS When the BYPASS instruction is loaded in the instruction register and the TAP is placed in a Shift-DR state, the bypass register is placed between the TDI and TDO pins. The advantage of the BYPASS instruction is that it shortens the boundary scan path when multiple devices are connected together on a board. EXTEST The EXTEST instruction enables the preloaded data to be driven out through the system output pins. This instruction also selects the boundary scan register to be connected for serial access between the TDI and TDO in the shift-DR controller state.
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EXTEST OUTPUT BUS TRI-STATE IEEE Standard 1149.1 mandates that the TAP controller be able to put the output bus into a tri-state mode. The boundary scan register has a special bit located at bit #89 (for 165-FBGA package) or bit #138 (for 209 FBGA package). When this scan cell, called the "extest output bus tri-state", is latched into the preload register during the "Update-DR" state in the TAP controller, it directly controls the state of the output (Q-bus) pins, when the EXTEST is entered as the current instruction. When HIGH, it enables the output buffers to drive the output bus. When LOW, this bit places the output bus into a High-Z condition. This bit can be set by entering the SAMPLE/PRELOAD or EXTEST command, and then shifting the desired bit into that cell, during the "Shift-DR" state. During "Update-DR", the value loaded into that shift-register cell latches into the preload register. When the EXTEST instruction is entered, this bit directly controls the output Q-bus pins. Note that this bit is pre-set HIGH to enable the output when the device is powered-up, and also when the TAP controller is in the "Test-Logic-Reset" state. Reserved These instructions are not implemented but are reserved for future use. Do not use these instructions.
TAP Timing
1 Test Clock (TCK)
t TMSS
2
3
4
5
6
t TH t TMSH
t
TL
t CYC
Test Mode Select (TMS)
t TDIS t TDIH
Test Data-In (TDI)
t TDOV t TDOX
Test Data-Out (TDO) DON'T CARE UNDEFINED
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TAP AC Switching Characteristics
Over the Operating Range[10, 11] Parameter Clock tTCYC tTF tTH tTL Output Times tTDOV tTDOX Setup Times tTMSS tTDIS tCS Hold Times tTMSH tTDIH tCH TMS Hold after TCK Clock Rise TDI Hold after Clock Rise Capture Hold after Clock Rise 5 5 5 ns ns ns TMS Setup to TCK Clock Rise TDI Setup to TCK Clock Rise Capture Setup to TCK Rise 5 5 5 ns ns ns TCK Clock LOW to TDO Valid TCK Clock LOW to TDO Invalid 0 10 ns ns TCK Clock Cycle Time TCK Clock Frequency TCK Clock HIGH time TCK Clock LOW time 20 20 50 20 ns MHz ns ns Description Min Max Unit
Notes: 10. tCS and tCH refer to the setup and hold time requirements of latching data from the boundary scan register. 11. Test conditions are specified using the load in TAP AC test Conditions. tR/tF = 1 ns.
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3.3V TAP AC Test Conditions
Input pulse levels ................................................ VSS to 3.3V Input rise and fall times ................................................... 1 ns Input timing reference levels ...........................................1.5V Output reference levels...................................................1.5V Test load termination supply voltage...............................1.5V
2.5V TAP AC Test Conditions
Input pulse levels................................................. VSS to 2.5V Input rise and fall time .....................................................1 ns Input timing reference levels......................................... 1.25V Output reference levels ............................................... .1.25V Test load termination supply voltage ............................ 1.25V
3.3V TAP AC Output Load Equivalent
1.5V 50 TDO Z O= 50 20pF
2.5V TAP AC Output Load Equivalent
1.25V 50 TDO Z O= 50 20pF
TAP DC Electrical Characteristics And Operating Conditions
(0C < TA < +70C; VDD = 3.135 to 3.6V unless otherwise noted)[12] Parameter VOH1 VOH2 VOL1 VOL2 VIH VIL IX Description Output HIGH Voltage Test Conditions IOH = -4.0 mA, VDDQ = 3.3V IOH = -1.0 mA, VDDQ = 2.5V Output HIGH Voltage IOH = -100 A IOL = 8.0 mA IOL = 1.0 mA Output LOW Voltage IOL = 100 A VDDQ = 3.3V VDDQ = 2.5V Output LOW Voltage VDDQ = 3.3V VDDQ = 2.5V VDDQ = 3.3V VDDQ = 2.5V Input HIGH Voltage VDDQ = 3.3V VDDQ = 2.5V Input LOW Voltage VDDQ = 3.3V VDDQ = 2.5V Input Load Current GND < VIN < VDDQ 2.0 1.7 -0.3 -0.3 -5 Min 2.4 2.0 2.9 2.1 0.4 0.4 0.2 0.2 VDD + 0.3 VDD + 0.3 0.8 0.7 5 Max Unit V V V V V V V V V V V V A
Note: 12. All voltages referenced to VSS (GND).
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Identification Register Definitions
Instruction Field Revision Number (31:29) Device Depth (28:24)
[13]
CY7C1461AV33 CY7C1463AV33 CY7C1465AV33 (1M x 36) (2M x 18) (512K x 72) 000 01011 001001 100111 00000110100 1 000 01011 001001 010111 00000110100 1 000 01011 001001 110111 00000110100 1
Description Describes the version number Reserved for internal use Defines memory type and architecture Defines width and density Allows unique identification of SRAM vendor Indicates the presence of an ID register
Architecture/Memory Type (23:18) Bus Width/Density(17:12) Cypress JEDEC ID Code (11:1) ID Register Presence Indicator (0)
Scan Register Sizes
Register Name Instruction Bypass ID Boundary Scan Order (165-Ball FBGA package) Boundary Scan Order (209-Ball FBGA package) Bit Size (x36) 3 1 32 89 - Bit Size (x18) 3 1 32 89 - Bit Size (x72) 3 1 32 - 138
Identification Codes
Instruction EXTEST IDCODE SAMPLE Z RESERVED SAMPLE/PRELOAD RESERVED RESERVED BYPASS Code 000 001 010 011 100 101 110 111 Description Captures IO ring contents. Places the boundary scan register between TDI and TDO. Forces all SRAM outputs to High-Z state. Loads the ID register with the vendor ID code and places the register between TDI and TDO. This operation does not affect SRAM operations. Captures IO ring contents. Places the boundary scan register between TDI and TDO. Forces all SRAM output drivers to a High-Z state. Do Not Use: This instruction is reserved for future use. Captures IO ring contents. Places the boundary scan register between TDI and TDO. Does not affect SRAM operation. Do Not Use: This instruction is reserved for future use. Do Not Use: This instruction is reserved for future use. Places the bypass register between TDI and TDO. This operation does not affect SRAM operations.
Note: 13. Bit #24 is "1" in the ID Register Definitions for both 2.5V and 3.3V versions of this device.
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165-Ball FBGA Boundary Scan Order [14]
CY7C1461AV33 (1M x 36), CY7C1463AV33 (2M x 18) Bit# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 Ball ID N6 N7 N10 P11 P8 R8 R9 P9 P10 R10 R11 H11 N11 M11 L11 K11 J11 M10 L10 K10 J10 H9 H10 G11 F11 Bit# 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Ball ID E11 D11 G10 F10 E10 D10 C11 A11 B11 A10 B10 A9 B9 C10 A8 B8 A7 B7 B6 A6 B5 A5 A4 B4 B3 Bit# 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 Ball ID A3 A2 B2 C2 B1 A1 C1 D1 E1 F1 G1 D2 E2 F2 G2 H1 H3 J1 K1 L1 M1 J2 K2 L2 M2 Bit# 76 77 78 79 80 81 82 83 84 85 86 87 88 89 Ball ID N1 N2 P1 R1 R2 P3 R3 P2 R4 P4 N5 P6 R6 Internal
Note: 14. Bit# 89 is preset HIGH.
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209-Ball FBGA Boundary Scan Order [15]
CY7C1465AV33 (512K x 72) Bit# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 Ball ID W6 V6 U6 W7 V7 U7 T7 V8 U8 T8 V9 U9 P6 W11 W10 V11 V10 U11 U10 T11 T10 R11 R10 P11 P10 N11 N10 M11 M10 L11 L10 K11 M6 L6 J6 Bit# 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 Ball ID F6 K8 K9 K10 J11 J10 H11 H10 G11 G10 F11 F10 E10 E11 D11 D10 C11 C10 B11 B10 A11 A10 C9 B9 A9 D8 C8 B8 A8 D7 C7 B7 A7 D6 G6 Bit# 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 Ball ID H6 C6 B6 A6 A5 B5 C5 D5 D4 C4 A4 B4 C3 B3 A3 A2 A1 B2 B1 C2 C1 D2 D1 E1 E2 F2 F1 G1 G2 H2 H1 J2 J1 K1 N6 Bit# 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 Ball ID K3 K4 K6 K2 L2 L1 M2 M1 N2 N1 P2 P1 R2 R1 T2 T1 U2 U1 V2 V1 W2 W1 T6 U3 V3 T4 T5 U4 V4 W5 V5 U5 Internal
Note: 15. Bit# 138 is preset HIGH.
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Maximum Ratings
Exceeding maximum ratings may impair the useful life of the device. These user guidelines are not tested. Storage Temperature ................................. -65C to +150C Ambient Temperature with Power Applied............................................. -55C to +125C Supply Voltage on VDD Relative to GND........ -0.5V to +4.6V Supply Voltage on VDDQ Relative to GND ...... -0.5V to +VDD DC Voltage Applied to Outputs in Tri-State........................................... -0.5V to VDDQ + 0.5V Range DC Input Voltage ................................... -0.5V to VDD + 0.5V Current into Outputs (LOW)......................................... 20 mA Static Discharge Voltage........................................... >2001V (MIL-STD-883, Method 3015) Latch-up Current..................................................... >200 mA
Operating Range
Ambient Temperature VDD VDDQ
Commercial 0C to +70C 3.3V -5%/+10% 2.5V - 5% to VDD Industrial -40C to +85C
Electrical Characteristics
Over the Operating Range[16, 17] Parameter Description Power Supply Voltage VDD IO Supply Voltage VDDQ VOH VOL VIH VIL IX Output HIGH Voltage Output LOW Voltage Input HIGH Voltage[16] Input LOW Voltage[16] Test Conditions for 3.3V IO for 2.5V IO for 3.3V IO, IOH = -4.0 mA for 2.5V IO, IOH = -1.0 mA for 3.3V IO, IOL = 8.0 mA for 2.5V IO, IOL = 1.0 mA for 3.3V IO for 2.5V IO for 3.3V IO for 2.5V IO GND VI VDDQ Min 3.135 3.135 2.375 2.4 2.0 Unit V V V V V 0.4 V 0.4 V VDD + 0.3V V VDD + 0.3V V 0.8 V 0.7 V 5 A A A A A A mA mA mA mA mA Max 3.6 VDD 2.625
IOZ IDD ISB1 ISB2 ISB3 ISB4
Input Leakage Current except ZZ and MODE Input Current of MODE Input = VSS Input = VDD Input Current of ZZ Input = VSS Input = VDD Output Leakage Current GND VI VDDQ, Output Disabled VDD Operating Supply VDD = Max., IOUT = 0 mA, 7.5 ns cycle, 133 MHz Current f = fMAX = 1/tCYC 10 ns cycle, 100 MHz VDD = Max, Device Deselected, 7.5 ns cycle, 133 MHz Automatic CE Power down VIN VIH or VIN VIL 10 ns cycle, 100 MHz Current--TTL Inputs f = fMAX, inputs switching VDD = Max, Device Deselected, All speeds Automatic CE Power down VIN 0.3V or VIN > VDD - 0.3V, Current--CMOS Inputs f = 0, inputs static VDD = Max, Device Deselected, 7.5 ns cycle, 133 MHz Automatic CE Power down or VIN 0.3V or VIN > VDDQ - 0.3V 10 ns cycle, 100 MHz Current--CMOS Inputs f = fMAX, inputs switching VDD = Max, Device Deselected, All Speeds Automatic CE Power down VIN VDD - 0.3V or VIN 0.3V, Current--TTL Inputs f = 0, inputs static
2.0 1.7 -0.3 -0.3 -5 -30
5 -5 -5 30 5 310 290 180 180 120
180 180 135
mA mA mA
Notes: 16. Overshoot: VIH(AC) < VDD +1.5V (Pulse width less than tCYC/2), undershoot: VIL(AC) > -2V (Pulse width less than tCYC/2). 17. TPower-up: Assumes a linear ramp from 0V to VDD(min.) within 200 ms. During this time VIH < VDD and VDDQ < VDD.
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Capacitance[18]
Parameter CIN CCLK CIO Description Input Capacitance Clock Input Capacitance Input/Output Capacitance Test Conditions TA = 25C, f = 1 MHz, VDD = 3.3V VDDQ = 2.5V 100 TQFP Max 6.5 3 5.5 165 FBGA Max 7 7 6 209 FBGA Max 5 5 7 Unit pF pF pF
Thermal Resistance[18]
Parameter JA JC Description Thermal Resistance (Junction to Ambient) Thermal Resistance (Junction to Case) Test Conditions Test conditions follow standard test methods and procedures for measuring thermal impedance, according to EIA/JESD51. 100 TQFP Package 25.21 2.28 165 FBGA Package 20.8 3.2 209 FBGA Package 25.31 4.48 Unit C/W C/W
AC Test Loads and Waveforms
3.3V IO Test Load
OUTPUT Z0 = 50 3.3V OUTPUT RL = 50
R = 317 VDDQ GND R = 351 10%
ALL INPUT PULSES 90% 90% 10% 1ns
VT = 1.5V (a)
5 pF INCLUDING JIG AND SCOPE
1ns
(b)
R = 1667 VDDQ GND R = 1538 10%
(c)
ALL INPUT PULSES 90% 90% 10% 1ns
2.5V IO Test Load
OUTPUT Z0 = 50 2.5V OUTPUT RL = 50 VT = 1.25V
(a)
5 pF INCLUDING JIG AND SCOPE
1ns
(b)
(c)
Note: 18. Tested initially and after any design or process change that may affect these parameters.
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Switching Characteristics
Over the Operating Range[23, 24] 133 MHz Parameter tPOWER Clock tCYC tCH tCL tCDV tDOH tCLZ tCHZ tOEV tOELZ tOEHZ Setup Times tAS tALS tWES tCENS tDS tCES Hold Times tAH tALH tWEH tCENH tDH tCEH Address Hold After CLK Rise ADV/LD Hold After CLK Rise WE, BWX Hold After CLK Rise CEN Hold After CLK Rise Data Input Hold After CLK Rise Chip Enable Hold After CLK Rise 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 ns ns ns ns ns ns Address Setup Before CLK Rise ADV/LD Setup Before CLK Rise WE, BWX Setup Before CLK Rise CEN Setup Before CLK Rise Data Input Setup Before CLK Rise Chip Enable Setup Before CLK Rise 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 ns ns ns ns ns ns Clock Cycle Time Clock HIGH Clock LOW 7.5 2.5 2.5 10 3.0 3.0 ns ns ns
[19]
100 MHz Min 1 Max Unit ms
Description
Min 1
Max
Output Times Data Output Valid After CLK Rise Data Output Hold After CLK Rise Clock to Clock to Low-Z[20, 21, 22] High-Z[20, 21, 22] 2.5 2.5 3.8 3.0 0 3.0 0 4.0 6.5 2.5 2.5 0 4.5 3.8 8.5 ns ns ns ns ns ns ns
OE LOW to Output Valid OE LOW to Output Low-Z[20, 21, 22] OE HIGH to Output High-Z[20, 21, 22]
Notes: 19. This part has a voltage regulator internally; tPOWER is the time that the power needs to be supplied above VDD(minimum) initially, before a read or write operation can be initiated. 20. tCHZ, tCLZ,tOELZ, and tOEHZ are specified with AC test conditions shown in part (b) of AC Test Loads. Transition is measured 200 mV from steady-state voltage. 21. At any voltage and temperature, tOEHZ is less than tOELZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve High-Z prior to Low-Z under the same system conditions. 22. This parameter is sampled and not 100% tested. 23. Timing reference level is 1.5V when VDDQ = 3.3V and is 1.25V when VDDQ = 2.5V. 24. Test conditions shown in (a) of AC Test Loads unless otherwise noted.
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Switching Waveforms
Read/Write Waveforms[25, 26, 27]
1 CLK
t CENS t CENH
2
t CY C
3
4
5
6
7
8
9
10
t CH
t CL
CEN
t CES t CEH
CE ADV/LD WE BW X ADDRESS
t AS
A1
t AH
A2
A3
t CDV t CLZ
A4
t DOH Q(A3) Q(A4) t OEHZ t OEV
A5
t CHZ Q(A4+1)
A6
A7
DQ
t DS
D(A1) t DH
D(A2)
D(A2+1)
D(A5)
Q(A6)
D(A7)
OE COM M AND
W RITE D(A1) W RITE D(A2) BURST W RITE D(A2+1) READ Q(A3) READ Q(A4) BURST READ Q(A4+1)
t OELZ
t DOH
W RITE D(A5)
READ Q(A6)
W RITE D(A7)
DESELECT
DON'T CARE
UNDEFINED
Notes: 25. For this waveform ZZ is tied LOW. 26. When CE is LOW, CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH, CE1 is HIGH or CE2 is LOW or CE3 is HIGH. 27. Order of the Burst sequence is determined by the status of the MODE (0 = Linear, 1 = Interleaved). Burst operations are optional.
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Switching Waveforms (continued)
NOP, STALL and DESELECT Cycles[25, 26, 28]
1 CLK CEN CE ADV/LD WE BW [A:D] ADDRESS DQ COMMAND
WRITE D(A1)
2
3
4
5
6
7
8
9
10
A1
A2 D(A1)
READ Q(A2) STALL
A3 Q(A2)
READ Q(A3)
A4 Q(A3)
WRITE D(A4) STALL
A5
t CHZ
D(A4)
t DOH NOP READ Q(A5)
Q(A5)
DESELECT CONTINUE DESELECT
DON'T CARE
UNDEFINED
Note: 28. The IGNORE CLOCK EDGE or STALL cycle (Clock 3) illustrates CEN being used to create a pause. A write is not performed during this cycle.
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Switching Waveforms (continued)
ZZ Mode Timing[29, 30]
CLK
t ZZ t ZZREC
ZZ
t ZZI
I
SUPPLY I DDZZ t RZZI DESELECT or REA D Only
A LL INPUTS (except ZZ)
Outputs (Q)
High-Z
DON'T CA RE
Notes: 29. Device must be deselected when entering ZZ mode. See truth table for all possible signal conditions to deselect the device. 30. DQs are in High-Z when exiting ZZ sleep mode.
Document #: 38-05356 Rev. *F
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CY7C1461AV33 CY7C1463AV33 CY7C1465AV33
Ordering Information
Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or visit www.cypress.com for actual products offered. Speed (MHz) 133 Ordering Code CY7C1461AV33-133AXC CY7C1463AV33-133AXC CY7C1461AV33-133BZC CY7C1463AV33-133BZC CY7C1461AV33-133BZXC CY7C1463AV33-133BZXC CY7C1465AV33-133BGC CY7C1465AV33-133BGXC CY7C1461AV33-133AXI CY7C1463AV33-133AXI CY7C1461AV33-133BZI CY7C1463AV33-133BZI CY7C1461AV33-133BZXI CY7C1463AV33-133BZXI CY7C1465AV33-133BGI CY7C1465AV33-133BGXI 100 CY7C1461AV33-100AXC CY7C1463AV33-100AXC CY7C1461AV33-100BZC CY7C1463AV33-100BZC CY7C1461AV33-100BZXC CY7C1463AV33-100BZXC CY7C1465AV33-100BGC CY7C1465AV33-100BGXC CY7C1461AV33-100AXI CY7C1463AV33-100AXI CY7C1461AV33-100BZI CY7C1463AV33-100BZI CY7C1461AV33-100BZXI CY7C1463AV33-100BZXI CY7C1465AV33-100BGI CY7C1465AV33-100BGXI 51-85167 209-Ball Fine-Pitch Ball Grid Array (14 x 22 x 1.76 mm) 209-Ball Fine-Pitch Ball Grid Array (14 x 22 x 1.76 mm) Pb-Free 51-85165 165-Ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-Free 51-85165 165-Ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) 51-85167 209-Ball Fine-Pitch Ball Grid Array (14 x 22 x 1.76 mm) 209-Ball Fine-Pitch Ball Grid Array (14 x 22 x 1.76 mm) Pb-Free 51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-Free lndustrial 51-85165 165-Ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-Free 51-85165 165-Ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) 51-85167 209-Ball Fine-Pitch Ball Grid Array (14 x 22 x 1.76 mm) 209-Ball Fine-Pitch Ball Grid Array (14 x 22 x 1.76 mm) Pb-Free 51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-Free Commercial 51-85165 165-Ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-Free 51-85165 165-Ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) 51-85167 209-Ball Fine-Pitch Ball Grid Array (14 x 22 x 1.76 mm) 209-Ball Fine-Pitch Ball Grid Array (14 x 22 x 1.76 mm) Pb-Free 51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-Free lndustrial 51-85165 165-Ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-Free 51-85165 165-Ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) Package Diagram Part and Package Type Operating Range Commercial
51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-Free
Document #: 38-05356 Rev. *F
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CY7C1461AV33 CY7C1463AV33 CY7C1465AV33
Package Diagrams
Figure 1. 100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm), 51-85050
16.000.20 14.000.10
100 1 81 80
1.400.05
0.300.08
22.000.20
20.000.10
0.65 TYP.
30 31 50 51
121 (8X)
SEE DETAIL
A
0.20 MAX. 1.60 MAX. 0 MIN. SEATING PLANE 0.25 GAUGE PLANE STAND-OFF 0.05 MIN. 0.15 MAX.
NOTE: 1. JEDEC STD REF MS-026 2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in (0.25 mm) PER SIDE BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH 3. DIMENSIONS IN MILLIMETERS
0-7
R 0.08 MIN. 0.20 MAX.
0.600.15 0.20 MIN. 1.00 REF.
DETAIL
51-85050-*B
A
Document #: 38-05356 Rev. *F
0.10
R 0.08 MIN. 0.20 MAX.
Page 28 of 31
CY7C1461AV33 CY7C1463AV33 CY7C1465AV33
Package Diagrams (continued)
Figure 2. 165-Ball FBGA (15 x 17 x 1.4 mm), 51-85165
BOTTOM VIEW TOP VIEW O0.05 M C PIN 1 CORNER O0.25 M C A B
PIN 1 CORNER
O0.450.05(165X)
1 2 3 4 5 6 7 8 9 10 11 11 10 9 8 7 6 5 4 3 2 1
A B
A B
D E F G
1.00
C
C D E F G
17.000.10
H J K
14.00
H J K
M N P R
7.00
L
L M N P R
A 5.00 10.00 0.530.05 0.25 C
+0.05 -0.10
1.00
0.35
0.15 C
B 0.15(4X)
15.000.10
SEATING PLANE C 0.36 1.40 MAX.
51-85165-*A
Document #: 38-05356 Rev. *F
Page 29 of 31
CY7C1461AV33 CY7C1463AV33 CY7C1465AV33
Package Diagrams (continued)
Figure 3. 209-Ball FBGA (14 x 22 x 1.76 mm), 51-85167
51-85167-**
NoBL and No Bus Latency are trademarks of Cypress Semiconductor Corporation. ZBT is a trademark of Integrated Device Technology, Inc. All product and company names mentioned in this document are the trademarks of their respective holders.
Document #: 38-05356 Rev. *F
Page 30 of 31
(c) Cypress Semiconductor Corporation, 2004-2007. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
CY7C1461AV33 CY7C1463AV33 CY7C1465AV33
Document History Page
Document Title: CY7C1461AV33/CY7C1463AV33/CY7C1465AV33 36-Mbit (1M x 36/2 M x 18/512K x 72) Flow-Through SRAM with NoBLTM Architecture Document Number: 38-05356 REV. ** ECN NO. 254911 Issue Date See ECN Orig. of Change SYT Description of Change New data sheet Part number changed from previous revision. New and old part number differ by the letter "A" Removed 150- and 117-MHz Speed Bins Changed JA and JC from TBD to 25.21 and 2.58 C/W, respectively, for TQFP package Added Pb-free information for 100-pin TQFP, 165 FBGA and 209 FBGA packages Added "Pb-free BG and BZ packages availability" below the Ordering Information Changed H9 pin from VSSQ to VSS on the Pin Configuration table for 209 FBGA Changed the test condition from VDD = Min. to VDD = Max for VOL in the Electrical Characteristics table Replaced the TBD's for IDD, ISB1, ISB2, ISB3 and ISB4 to their respective values Replaced TBD's for JA and JC to their respective values on the Thermal Resistance table for 165 FBGA and 209 FBGA Packages Changed CIN, CCLK and CIO to 6.5, 3 and 5.5 pF from 5, 5 and 7 pF for TQFP Package Removed "Pb-free BG packages availability" comment below the Ordering Information Modified Address Expansion balls in the pinouts for 165 FBGA and 209 FBGA Packages according to JEDEC standards and updated the Pin Definitions accordingly Modified VOL, VOH test conditions Replaced TBD to 100 mA for IDDZZ Changed CIN, CCLK and CIO to 7, 7and 6 pF from 5, 5 and 7 pF for 165 FBGA Package Added Industrial Temperature Grade Changed ISB2 and ISB4 from 100 and 110 mA to 120 and 135 mA respectively Updated the Ordering Information by shading and unshading MPNs according to availability Converted from Preliminary to Final Changed address of Cypress Semiconductor Corporation on Page# 1 from "3901 North First Street" to "198 Champion Court" Changed IX current value in MODE from -5 & 30 A to -30 & 5 A respectively and also Changed IX current value in ZZ from -30 & 5 A to -5 & 30 A respectively on page# 20 Modified test condition from VIH < VDD to VIH < VDD Modified "Input Load" to "Input Leakage Current except ZZ and MODE" in the Electrical Characteristics Table Replaced Package Name column with Package Diagram in the Ordering Information table Replaced Package Diagram of 51-85050 from *A to *B Updated the Ordering Information Added the Maximum Rating for Supply Voltage on VDDQ Relative to GND. Changed tTH, tTL from 25 ns to 20 ns and tTDOV from 5 ns to 10 ns in TAP AC Switching Characteristics table. Updated the Ordering Information table.
*A
300131
See ECN
SYT
*B
320813
See ECN
SYT
*C
331551
See ECN
SYT
*D
417547
See ECN
RXU
*E
473650
See ECN
VKN
*F
1274733 See ECN VKN/AESA Corrected typo in the "NOP, STALL and DESELECT Cycles" waveform
Document #: 38-05356 Rev. *F
Page 31 of 31

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